The present invention generally relates to MOS switched capacitor filtering systems and, more particularly, to an improved MOS switched capacitor circuit configuration which is particularly well adapted for use in low supply voltage applications.
Switched capacitor circuits utilize metal-oxide-semiconductor (MOS) transistors and capacitors to simulate the circuit behavior of a resistor. Switched capacitor filtering systems offer a significant improvement over conventional resistor-capacitor (RC) filters since the resistance values of integrated resistors are not highly controllable in MOS integrated circuit technology, whereas the ratio between MOS capacitors is reproducible accurate to within 0.1%.
A switched capacitor integrator circuit 10 is shown in FIG. 1 in accordance with the prior art. Operational amplifier 19, having its non-inverting terminal tied to analog ground voltage V.sub.AG, is used in the inverting mode with capacitor C2 providing negative feedback from the op-amp output at V.sub.OUT to the op-amp inverting input. The switched capacitor C1 and its associated switches simulate the function of a series input resistor. When charging switches 11 and 14, controlled by clock signal .phi..sub.1, and discharge switches 12 and 13, controlled by clock signal .phi..sub.2, are alternately opened and closed at a clock rate f.sub.c, then the switched capacitor circuit would give the same average current as a resistor having a value: EQU R=1/C.multidot.f.sub.c
If the switch rate is much larger than the signal frequencies of interest, then the time sampling of the signal can be ignored, and the transfer function of the circuit would be: ##EQU1##
FIG. 2 illustrates an alternate switched capacitor circuit configuration, also known in the art. Auto-zeroed gain stage 20 is used to provide signal amplification while cancelling out the detrimental effect of the amplifier offset. Switches 22, 23, and 25 are closed during the .phi..sub.2 clock cycle, and the offset present at the output of amplifier 29 is stored on capacitors C1 and C2. During the .phi..sub.1 clock cycle, C1 is configured as an input capacitor (via closing switch 21) while C2 is configured as a feedback capacitor (via closing switch 24). Over a complete cycle of operation, the circuit exhibits a frequency dependent gain of -C1/C2 with excellent amplifier offset cancellation. Hence, switched capacitor circuits are not only limited to filtering applications.
In the circuit configuration of FIG. 2, gain device 29 may alternately be a comparator. In this case, capacitor C2 would be set equal to zero (open circuit) to provide an "infinite" gain. The circuit would then serve the function of comparing the input signal voltage V.sub.IN to the analog ground voltage V.sub.AG. Numerous additional switched capacitor circuit configurations are possible to perform other circuit functions.
FIG. 3 illustrates the several alternative transmission gate configurations which may be used for the switches of FIGS. 1 and 2. FIG. 3A illustrates the first switch configuration 30, a single N-channel enhancement mode MOS transistor. An input signal to be switched is applied to source (S) terminal 31. The clock signal .phi..sub.1 is applied to the gate (G) terminal 34. The output signal is then available at the the drain (D) terminal 33 when the switch is conducting (when .phi.1 is high). In this and the following descriptions of transmission gate configurations, the terms source and drain are interchangeable, since the MOS transistor is a bilaterally symmetrical device. Whether a terminal functions as a source or drain depends on the relative potential of the two terminals.
If the N-channel transistor is formed in an N-substrate, then a P-tub or P-well constitutes the bulk (B) terminal 32. Conversely, if the N-channel device is formed in a P-substrate, the P-substrate itself constitutes the bulk. It is standard practice to connect all the P-tubs in an N-substrate CMOS integrated circuit to the most negative voltage in the circuit. Hence, bulk terminal 32 is shown connected to ground, V.sub.SS.
The operating characteristics of N-channel device 30 are shown in FIG. 4A by curve 52 labeled NMOS. The MOSFET's "on" resistance R is graphed versus the signal voltage V.sub.SIG. It can be seen that the operating range of a single N-channel device is limited by the maximum allowable "on" resistance. The small-signal on resistance R, or resistance across the device, is a nonlinear function proportional to: EQU 1/(V.sub.DD -V.sub.SIG -V.sub.Tn)
where V.sub.SIG is the input signal voltage, and V.sub.Tn is the N-channel device threshold. V.sub.Tn is a monotonically increasing function of (V.sub.SIG -V.sub.BULK). As the input signal voltage V.sub.SIG increases, the resistance curve 52 of the N-channel MOS device approaches an asymptote shown by vertical line 54 at the value of V.sub.SIG where the quantity (V.sub.DD -V.sub.SIG -V.sub.Tn) equals zero. It can be seen from the graph that the high on resistance of a single NMOS device would prohibit a large voltage swing. To obtain a maximum signal swing, the analog ground voltage V.sub.AG is typically set at one-half of the supply voltage V.sub.DD.
As one solution to this high on resistance problem, the prior art has utilized complementary MOS (CMOS) devices as shown in FIG. 3B. CMOS switch 35 is comprised of N-channel MOSFET 36 having its source (S) and drain (D) connected in parallel to the source and drain of P-channel MOSFET 38. Clock signals .phi..sub.1 and .phi..sub.1, applied to the respective gate (G) terminals, are in phase but have opposite polarity. Hence, both transistors will be conducting at the same time.
Returning to FIG. 4A, N-channel transistor 36 exhibits resistance curve 52 (labeled NMOS), while P-channel transistor switch 38 exhibits the resistance curve 56 (labeled PMOS). The composite resistance characteristic of the CMOS device is derived from the parallel combination of the NMOS resistance (curve 52) and the PMOS resistance (curve 56). This CMOS switch arrangement results in an operating signal range extending from V.sub.SS to V.sub.DD, provided that PMOS asymptote 58 occurs at a sufficiently lower voltage than NMOS asymptote 54 such that the maximum resistance of the CMOS switch is acceptable.
A further advantage of using CMOS devices is that the effect of parasitic charge injection caused when the N-channel device turns off is effectively cancelled by the corresponding charge injection caused when the P-channel turns off--if the devices are of the same size. In practice, however, this net charge cancellation is difficult to achieve without additional clocking circuitry and a corresponding decrease in operating speed. If both devices do not turn off at exactly the same time, the parasitic charge injected by the device turning off first will be swept through the device which is still on, and will still contribute to a net charge injection. Furthermore, the channel charge of a MOS device is a function of its threshold voltage as well as its size. It is well known that N-channel thresholds cannot be expected to have precisely the same absolute value as P-channel thresholds on a given wafer.
Referring now to FIG. 4B, the worst case resistance characteristics of CMOS transmission gate 35 of FIG. 3B is illustrated. The absolute value of the on resistance of a MOSFET can exhibit large variations with changes in temperature and process parameters, and the on resistance is not constant with changes in the applied signal voltage. Under worst case processing and temperature conditions, the on resistance of the switch can become excessively high or even infinite. This phenomenon is particularly apparent under low supply voltage conditions where the transistors operate under reduced gate-to-source drive. As the graph illustrates, the on resistance of the NMOS transistor follows curve 62 to approach asymptote 64. Similarly, the on resistance of the PMOS transistor follows curve 66 to approach asymptote 68. This worst case CMOS response results in a region of infinite switch resistance between the two asymptotes.
More specifically, the N-channel asymptote is given by the equation: EQU (V.sub.DD -V.sub.SIG -V.sub.Tn)=0
and the P-channel asymptote is given by the equation: EQU (V.sub.SIG -V.sub.Tp)=0
where V.sub.Tp, the corresponding P-channel device threshold, is a function of (V.sub.BULKp -V.sub.SIG). It should be noted that the N-channel asymptote decreases linearly with V.sub.DD, while the P-channel asymptote decreases only as a function of the dependence of V.sub.Tp on V.sub.DD. This dependence is less than first order, which indicates that the infinite resistance condition shown in FIG. 4B will occur for any CMOS transmission gate at a low enough value of V.sub.DD. The particular value at which the condition occurs depends on the thresholds of the devices, which in turn depends on processing parameters and operating temperature. The infinite resistance condition generally occurs for values of V.sub.SIG near mid-supply, which is the most useful operating range of an analog circuit. A CMOS switch having the characteristics shown in FIG. 4B is essentially useless for most analog signal processing applications.
In an attempt to alleviate this problem, the "switched tub" transmission gate 40 shown in FIG. 3C was developed. N-channel transistor 42 and P-channel transistor 44 comprise the transmission gate switching transistors, and have their gates (G) coupled to inverse control signals .phi..sub.1 and .phi..sub.1, respectively. Two additional transistors, P-channel MOSFET 46 and N-channel MOSFET 48, are coupled to the bulk (B) terminal of N-channel transistor 42 to switch the tub of the N-channel device either to ground potential or to the output potential. When control signal .phi..sub.1 is high, transistors 42, 44, and 46 are conducting, such that the bulk of N-channel transistor 42 is connected to one side of the switch (the transmission gate output terminal in this case). When the bulk is connected to the same potential as the signal being switched, the threshold of the N-channel device is lowered, and the asymptote is shifted to a higher value of V.sub.SIG. The extended operating range achieved by switching the tub of the N-channel device can be seen from FIG. 4C, which compares the resistance curves of a single N-channel device (curve 62) and a switched tub N-channel device (curve 72).
Although the switched tub switch exhibits an acceptable on resistance at low supply voltages, there are still several disadvantages regarding its use in switched capacitor circuits. First, switching the tub requires extra transistors which take up more room on the integrated circuit. Second, as noted by Petersen in U.S. Pat. No. 4,473,761, parasitic capacitances from the gate/drain and gate/source regions of MOS transistors produce a parasitic charge injection which is difficult to predict and cancel in switched tub switches.
A further problem, noted by Ahuja, et al., in U.S. Pat. No. 4,442,529, is that of noise susceptibility. Switched capacitor filter circuits typically have high-impedance summing node points which are particularly susceptible to power supply noise signals. In the integrator circuit of FIG. 1 and the gain stage circuit of FIG. 2, the critical summing junction is the inverting input terminal of the op-amps. Power supply noise can be capacitively coupled from the substrate to the switches which are connected to the high impedance inverting terminal of the op-amp (summing junction). If the switch is a MOS transistor built directly into the substrate (i.e., P-channel in an N-substrate), the coupling is between the source/drain of the transistor and the substrate. If the switch is a switched tub device, the coupling is between the substrate and the tub.
Power supply noise coupling into the high impedance nodes can be effectively eliminated by utilizing single transistor devices having their own isolated tubs--such as NMOS in a P-well process or PMOS in an N-well process--with the tubs hardwired to a clean supply. The tubs then function to shield the source/drain of the transistor from the substrate. The problem with this approach is that, with V.sub.AG set to one-half V.sub.DD, the N-channel devices at the summing junction will not turn on under low supply voltage conditions (i.e., V.sub.DD =5 VDC or less, single-supply).
Therefore, a need exists for a switched capacitor circuit configuration adapted for use in low voltage applications which addresses the problems of switch charge injection, high on resistance, and noise susceptibility.